In an effort to develop new semiconductor packaging technologies, DuPont Wafer Level Packaging Solutions, part of DuPont Electronic Technologies, has signed a joint-development agreement with Nippon Kayaku Co. Ltd. (NKC) and its wholly owned subsidiary, MicroChem Corp. Wafer level packaging refers to the technology of packaging an integrated circuit at wafer level, instead of the traditional process of assembling the package of each individual unit after wafer dicing. The electronic materials developed under the agreement will be new advanced photodefinable epoxy-based materials. They will be directed at wafer level packaging, 3D and through-silicon via (TSV) semiconductor packaging applications that are transforming electronics to make them smaller, lighter weight, more functional and more cost-effective.
"Combining the expertise of Nippon Kayaku and MicroChem in advanced epoxy resins and formulation, with DuPont coating technology, material science and electronic applications knowledge means that we can generate a series of enabling materials faster," said Mats Ehlin, global business manager, DuPont Wafer Level Packaging Solutions. DuPont estimates the materials market for wafer level packaging, 3D and TSV will grow from about USD 100 mln in 2009, to more than USD 600 mln in 2013, and could as much as double to USD 1.2 bln by 2015. Wafer level packaging is spreading rapidly as a way to significantly improve the efficiency and reduce the size of semiconductor packages.